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1 publication order number : LC88FC3J0A/d ? semiconductor components industries, llc, 2016 january 2016 - rev. 1 ordering information see detailed ordering and shipping info rmation on page 48 of this data sheet. www.onsemi.com LC88FC3J0A LC88FC3J0A is a 16-bit microcontroller with 640k-byte flash rom/47.5k- byte ram in 100-pin package. main f eatures are infrared remote controller receiver circuit (supports ppm and manc hester encoding), 16 channels of 12- bit resolution adc, internal reset circuit, crc circuit and etc. that are software friendly circuits and these peripheral ci rcuit can contribute to less external components. also, plenty of serial interface circuits (synchronous serial 3, i 2 c 3, uart 3) can communicate with other lsis and are suitable for home appliances and white goods whic h need complicated control. for software development, there is our original software development environment and with on-chip debugging function, it is easy to debug with user?s actual application. features ? 16-channel 12-bit resolution ad converter ? infrared remote controller receiver circuit ? crc operating circuit ? internal reset function performance ? 100ns (10.0mhz) v dd =2.7 to 3.6v ta= ? 40 ? c to +85 ? c function descriptions ? xstromy16 cpu - 4g-byte address space - general-purpose registers: 16 bits ? 16 registers ? ports - i/o ports 86 - power supply pins 8 (vss1 to vss4, vdd1 to vdd4) ? timer - 16-bit timers ? 8 - base timer serving as a time-of-day clock ? serial interfaces - synchronous si o interfaces ? 3 (with automatic transmission capability) - single master i 2 c/synchronous sio interface ? 2 - slave i 2 c/synchronous sio interface - asynchronous sio (uart) interfaces ? 3 ? multifrequency 12-bit pwm modules ? 16-channel 12-bit resolution ad converter ? watchdog timer ? infrared remote controller receiver circuit ? crc operating circuit ? real time clock ? system clock frequency divider ? cf oscillator circuit, crystal oscillator circuit, rc oscillator circuit ? 61-source 14-vector interrupt feature ? on-chip debugger function application ? home audio, white goods 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p41/int7 p42 p43/so1 p44/si1/sb1 p45/sck1 p46/pwm0a p47/pwm0b p27 p26/t5o p25/t4o p24/sm0do p23/sm0da p22/sm0ck vdd2 vss2 p21/int5 p20/int4 pd5 pd4 pd3 pd2 pd1 pd0 p17/u2tx p16/u2rx 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 pb6/sm1do p70/an8 p71/an9 p72/an10 p73/an11 p74/an12 p75/an13 p76/an14 p77/an15 v ss4 v dd 4 pa0/so4 pa1/si4/sb4 pa2/sck4 pa3/scs4 pa4/sl0c k pa5/sl0d a pa6/sl0do pa7 pc2/fil t p50/p5int0 p51/p5int1 p52/p5int2 p53/p5int3 p54/p5int4 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 pb5/sm1da pb4/sm1ck pb3 pb2 pb1 pb0 p37/t7o p36/t6o p35/u3tx p34/u3rx p33/int3 p32/int2/rmin p31/int1 p30/int0 p07/t0pwmh/u0brg p06/t0pwml p05/p05int p04/p04int p03/p0int p02/p0int p01/p0int p00/p0int vss3 vdd3 p40/int6 top view lc88fc2h0b p55/p5int5 p56/p5int6 p57/p5int7 test resb pc0/xt1 pc1/xt2 v ss 1 pc3/cf1 pc4/cf2 v dd 1 p60/an0 p61/an1 p62/an2 p63/an3 p64/an4 p65/an5 p66/an6 p67/an7 p10/so0 p11/si0/sb0 p12/sck0 p13/u0tx p14/t3ol/u0rx p15/t3oh 16-bit microcontroller 640k-byte flash rom / 47.5k-byte ram / 100-pin pin assignment (top view) * this product is licensed from s ilicon storage technology, inc. (usa). lc88fc3j0 a tqfp 100,14x14
LC88FC3J0A www.onsemi.com 2 function details ? xstromy16 cpu ? 4g-byte address space ? general-purpose registers : 16 bits ? 16 registers ? flash rom ? 655360 ? 8 bits ? programming voltage level : 2.7 to 3.6v. ? block-erasable in 2k byte units. ? data written in 2-byte units. ? ram ? 48640 ? 8 bits ? minimum instruction cycle time (tcyc) ? 100 ns (10 mhz), v dd = 2.7 to 3.6v ? ports ? normal withstand voltage i/o ports ports whose i/o direction can be designated in 1 bit units : 86 (p0n p1n, p2n, p3n, p4n, p5n, p6n, p7n, pan pb0 to pb6, pc2, pd0 to pd5) ? oscillation/normal withstand voltage i/o ports : 4 (pc0, pc1, pc3, pc4) ? reset pins : 1 (resb) ? test pins : 1 (test) ? power pins : 8 (v ss 1 to 4, v dd 1 to 4) ? timers ? timer 0 : 16-bit timer that supports pwm/toggle outputs <1> 5-bit prescaler <2> 8-bit pwm ? 2, 8-bit timer + 8-bit pwm mode selectable <3> clock source selectable from system clock, osc0, osc1, and internal rc oscillator. ? timer 1 : 16-bit timer with capture registers <1> 5-bit prescaler <2> may be divided into 2 channels of 8-bit timer <3> clock source selectable from system clock, osc0, osc1, and internal rc oscillator ? timer 2 : 16-bit timer with capture registers <1> 4-bit prescaler <2> may be divided into 2 channels of 8-bit timer <3> clock source selectable from system clock, osc0, osc1, and external events ? timer 3 : 16-bit timer that shpports pwm/toggle outputs <1> 8-bit prescaler <2> 8-bit timer ? 2ch or 8-bit timer+8-bit pwm mode selectable <3> clock source selectable from system clock, osc0, osc1, and external events ? timer 4 : 16-bit timer that supports toggle outputs <1> clock source selectable from system clock and prescaler 0 ? timer 5 : 16-bit timer that supports toggle output <1> clock source selectable from system clock and prescaler 0 ? timer 6 : 16-bit timer that supports toggle outputs <1> clock source selectable from system clock and prescaler 1 ? timer 7 : 16-bit timer that supports toggle output <1> clock source selectable from system clock and prescaler 1 *prescaler 0 and 1 are consisted of 4bits and can choose their clock source from osc0 or osc1. ? base timer <1> clock may be selected from osc0 (32.768 khz crystal oscillator) and frequency-divided output of system clock. <2> interrupts can be generated in 7 timing schemes.
LC88FC3J0A www.onsemi.com 3 ? real time clock <1> calender with jan. 1, 2000 to dec.31, 2799 including automatic leapyear calculation function. <2> consisted of indipendent second-minuit-hour-day-month-yeare-century counters. ? serial interfaces ? sio0 : 8-bit synchronous sio <1> lsb first/msb first mode selectable <2> supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable) <3> built-in 8-bit baudrate generator (4 tcyc to 512 tcyc transfer clocks) <4> continuous/automatic data transmission (9- to 32768-bit units specifiable) <5> interval function (intervals specifiable in 0 to 64tsck units) <6> wakeup function ? sio1 : 8-bit synchronous sio <1> lsb first/msb first mode selectable <2> supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable) <3> built-in 8-bit baudrate generator (4 tcyc to 512 tcyc transfer clocks) <4> continuous/automatic data transmission (9- to 32768-bit units specifiable) <5> interval function (intervals specifiable in 0 to 64tsck units) <6> wakeup function ? sio4 : 8-bit synchronous sio <1> lsb first/msb first mode selectable <2> supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable) <3> built-in 8-bit baudrate generator (4 tcyc to 512 tcyc transfer clocks) <4> continuous/automatic data transmission (9- to 32768-bit units specifiable) <5> interval function (intervals specifiable in 0 to 64tsck units) <6> wakeup function ? smiic0 : single master i 2 c/8-bit synchronous sio mode 0 : single-master mode communication mode 1 : synchronous 8-bit serial i/o (msb first) ? smiic1 : single master i 2 c/8-bit synchronous sio mode 0 : single-master mode communication mode 1 : synchronous 8-bit serial i/o (msb first) ? sliic0 : slave i 2 c/8-bit synchronous sio mode 0 : i 2 c slave mode communication mode 1 : synchronous 8-bit serial i/o (msb first) note: usable only with the external clock source
LC88FC3J0A www.onsemi.com 4 ? uart0 <1> data length : 8 bits (lsb first) <2> start bits : 1 bit <3> stop bits : 1 bit <4> parity bits : none/even parity/odd parity <5> transfer rate : 4/8 cycle <6> baudrate source clock: p07 input signal used as a 1 cycle signal (t0pwmh can be used as a clock source) or timer4 cycle. <7> full duplex communication note : the ?cycle? refers to one period of the baudrate clock source. ? uart2 <1> data length : 8 bits (lsb first) <2> start bits : 1 bit <3> stop bits : 1/2 bit <4> parity bits : none/even parity/odd parity <5> transfer rate : 8 to 4096 cycle <6> baudrate source clock: system clock/osc0/osc1/p26 input signal <7> wakeup function <8> full duplex communication note : the ?cycle? refers to one period of the baudrate clock source. ? uart3 <1> data length : 8 bits (lsb first) <2> start bits : 1 bit <3> stop bits : 1/2 bit <4> parity bits : none/even parity/odd parity <5> transfer rate : 8 to 4096 cycle <6> baudrate source clock: system clock/osc0/osc1/p36 input signal <7> wakeup function <8> full duplex communication note : the ?cycle? refers to one period of the baudrate clock source. ? ad converter <1> 12/8 bits resolution selectable <2> analog input: 16 channels <3> comparator mode ? pwm ? pwm0 : multifrequency 12-bit pwm ? 2 channels (pwm0a and pwm0b) <1> 2-channel pairs controlled independently of one another <2> clock source selectable from system clock or osc1 <3> 8-bit prescaler: tpwmr0= (prescaler value + 1) ? clock period <4> 8-bit fundamental wave pwm generator circuit + 4-bit additional pulse generator circuit <5> fundamental wave pwm mode fundamental wave period : 16 tpwmr0 to 256 tpwmr0 high pulse width : 0 to (fundamental wave period - tpwmr0) <6> fundamental wave + additional pulse mode fundamental wave period : 16 tpwmr0 to 256 tpwmr0 overall period : fundamental wave period ? 16 high pulse width : 0 to (fundamental wave period - tpwmr0) ? crc operating circuit ? watchdog timer <1> driven by the base timer + intern al watchdog timer dedicated counter <2> interrupt or reset mode selectable
LC88FC3J0A www.onsemi.com 5 ? infrared remote controller receiver circuit 1) noise rejection function (noise filter time constant: approx. 120 ? s when the 32.768khz crystal oscillator is selected as the reference clock source) 2) supports data encording systems such as ppm (pulse position modulation) and manchester encording 3) x?tal hold mode release function ? internal reset function ? power-on reset (por) function 1) por reset is generated only at power-on time. 2) the por release level can be selected through option configuration. ? low-voltage detection reset (lvd) function 1) lvd and por functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) the use/disuse of the lvd function and the low voltage threshold level can be selected by option configuration. ? interrupts (peripheral function) ? 61 sources (33 modules), 14 vector addresses <1> provides three levels (low (l), high (h), and high est (x)) of multiplex interrupt control. any interrupt requests of the level equal to or lower than the current interrupt are not accepted. <2> when interrupt requests to two or more vector ad dresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts . for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address interrupt module 1 08000h watchdog timer (1) 2 08004h base timer (2) 3 08008h timer 0 (2) 4 0800ch int0 (1) 5 08014h int1 (1) 6 08018h int2 (1) / timer 1 (2) / uart2 (4) 7 0801ch int3 (1) / timer 2 (4) / smiic0 (1) / sliic1 (1) 8 08020h int4 (1) / timer 3 (2) / infared remote control receiver(4) 9 08024h int5 (1) / timer 4 (1) / sio1 (2) 10 0802ch pwm0 (1) / smiic1(1) 11 08030h adc (1) / timer 5 (1) / sio4(2) 12 08034h int6 (1) / timer 6 (1) / uart 3 (4) 13 08038h int7 (1) / sio0 (2) / sio0(2) 14 0803ch port 0 (3) / port 5 (8) / rtc (1) / crc (1) ? 3 priority levels selectable ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? a number enclosed in parentheses denotes the number of sources. ? subroutine stack : ram area ? subroutine calls that automatically save psw, interrupt vector calls: 6 bytes ? subroutine calls that do not automatically save psw: 4 bytes ? multiplication/division instructions ? 16 bits 16 bits (4 tcyc execution time) ? 16 bits 16 bits (18 to 19 tcyc execution time) ? 32 bits 16 bits (18 to 19 tcyc execution time)
LC88FC3J0A www.onsemi.com 6 ? oscillator circuits ? rc oscillator circuit (internal) : for system clock ? cf oscillator circuit ( built-in rf circuit ) : for system clock( osc1 ) ? crystal oscillator circuit ( built-in rf circ uit ) : for low-speed system clock (osc0) ? slrc oscillator circuit (internal) : for system clock (in the case of exception processing) ? vco oscillator circuit : for timer3, 4, 5, 6, 7 clock ? system clock divider function ? can run on low current. ? 1/1 to 1/128 of the system clock frequency can be set. ? standby function ? halt mode : halts instruction execution while allo wing the peripheral circuits to continue operation. <1> oscillation is not stopped automatically. <2> released by a system reset or occurrence of an interrupt. ? hold mode : suspends instruction execution an d the operation of the peripheral circuits. <1> osc1, rc, and osc0 oscillations automatically stop. <2> there are six ways of releasing the hold mode: (1) setting the reset pin to the low level (2) setting at least one of the int0, int1, int2, in t4, int5, int6, and int7 pins to the specified level (3) having an interrupt source established at port 0 (4) having an interrupt source established at port 5 (5) having an interrupt established at sio0, sio1 or sio4 (6) having an interrupt established at uart2 or uart3 ? holdx mode : suspends instruction execution and the operation of the peripheral circuits except those which run on osc0. <1> osc1 and rc oscillations automatically stop. <2> osc0 maintains the state that is established when the holdx mode is entered. <3> there are nine ways of releasing the holdx mode. (1) setting the reset pin to the low level (2) setting at least one of the int0, int1, int2, int4, int5, int6,and int7 pins to the specified level (3) having an interrupt source established at port 0 (4) having an interrupt source established at port 5 (5) having an interrupt source established at the base timer circuit (6) having an interrupt established at sio0, sio1 or sio4 (7) having an interrupt established at uart2 or uatr3 (8) having an interrupt established at infared remote control receiver. (9) having an interrupt source estab lished at the real time clock circuit ? on-chip debugger function ? supports software debugging with the ic mounted on the target board. ? supports source line debugging and tracing functions, and breakpoint setting and real time display. ? single-wire communication ? package form ? tqfp100, 14 ? 14 : pb-free and halogen free type
LC88FC3J0A www.onsemi.com 7 ? development tools ? on-chip debugger : eocuif1 or eocuif2 + LC88FC3J0A ? programming board package programming board tqfp 100, 14 ? 14 w88f52tq ? flash rom programmer maker model supported version device on semiconductor single / gang programmer skk type c (sanyofws) application version after 1.08a chip data version after 2.51 lc88fc3x0 on-board single programmer fws-x16di type 3 application version after 1.08a chip data version after 2.51 lc88fc3x0
LC88FC3J0A www.onsemi.com 8 package dimensions unit : mm tqfp 100, 14x14 case 932an-01 issue o
LC88FC3J0A www.onsemi.com 9 pin assignment tqfp100,1414 (pb-free and halogen free type) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p55/p5int5 p56/p5int6 p57/p5int7 test resb pc0/xt1 pc1/xt2 v ss 1 pc3/cf1 pc4/cf2 v dd 1 p60/an0 p61/an1 p62/an2 p63/an3 p64/an4 p65/an5 p66/an6 p67/an7 p10/so0 p11/si0/sb0 p12/sck0 p13/u0tx p14/t3ol/u0rx p15/t3oh 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p41/int7 p42 p43/so1 p44/si1/sb1 p45/sck1 p46/pwm0a p47/pwm0b p27 p26/t5o p25/t4o p24/sm0do p23/sm0da p22/sm0ck vdd2 vss2 p21/int5 p20/int4 pd5 pd4 pd3 pd2 pd1 pd0 p17/u2tx p16/u2rx 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 pb6/sm1do p70/an8 p71/an9 p72/an10 p73/an11 p74/an12 p75/an13 p76/an14 p77/an15 v ss4 v dd 4 pa0/so4 pa1/si4/sb4 pa2sck4 pa3/scs4 pa4/sl0ck pa5/sl0da pa6/sl0do pa7 pc2/filt p50/p5int0 p51/p5int1 p52/p5int2 p53/p5int3 p54/p5int4 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 pb5/sm1da pb4/sm1ck pb3 pb2 pb1 pb0 p37/t7o p36/t6o p35/u3tx p34/u3rx p33/int3 p32/int2/rmin p31/int1 p30/int0 p07/t0pwmh/u0brg p06/t0pwml p05/p05int p04/p04int p03/p0int p02/p0int p01/p0int p00/p0int vss3 vdd3 p40/int6 top view LC88FC3J0A
LC88FC3J0A www.onsemi.com 10 system block diagram clock generator cf rc x?tal port 0 port 1 sio0 sio1 sliic0 timer 0 timer 1 timer 2 timer 3 port 2 port 3 port 4 port 5 uart0 port a timer 4 pwm0 on-chip debugger port 6 xstromy16 cpu ram flash rom base timer watchdog timer sio4 int0 to int7 timer 5 port 7 low speed rc uart2 timer 6 timer 7 smiic0 smiic1 uart3 ad da rtc port b port c port d vco pll lvd/por crc remote control receiver circuit
LC88FC3J0A www.onsemi.com 11 pin description pin name i/o description vss1, vss2, vss3, vss4 ? ? power sources vdd1, vdd2, vdd3, vdd4 ? + power sources port 0 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? hold release input (p00 to p03, p04, p05) ? port 0 interrupt input (p 00 to p03, p04, p05) ? pin functions p06 : timer 0l output p07 : timer 0l output/uart0 clock input p00 to p07 port 1 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? pin functions p10 : sio0 data output p11 : sio0 data input/pulse input/output p12 : sio0 clock input/output p13 : uart0 transmit p14 : timer 3l output/uart0 receive p15 : timer 3h output p16 : uart2 receive p17 : uart2 transmit p10 to p17 port 2 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? pin functions p20 : int4 input/hold release input/timer 3 event input/ timer 2l capture input/timer 2h capture input p21 : int5 input/hold release input/timer 3 event input/ timer 2l capture input/timer 2h capture input p22 : smiic0 clock input/output p23 : smiic0 bus input/output/data input p24 : smiic0 data output (used in 3-wire sio mode) p25 : timer 4 output p26 : timer 5 output interrupt acknowledge type int4, int5 : h level, l level, h edge, l edge, both edges p20 to p27 continued on next page.
LC88FC3J0A www.onsemi.com 12 continued from preceding page. pin name i/o description port 3 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? pin functions p30 : int0 input/hold releas e/timer 2l capture input p31 : int1 input/hold releas e/timer 2h capture input p32 : int2 input/hold release/timer 2 event input/timer 2l capture input/ infrared remote controller receiver input p33 : int3 input/hold release/timer 2 event input/timer 2h capture input p34 : uart3 receive p35 : uart3 transmit p36 : timer 6 output p37 : timer 7 output interrupt acknowledge type int0 to int3 : h level, l level, h edge, l edge, both edges p30 to p37 port 4 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? pin functions p40 : int6 input/ hold release input p41 : int7 input/ hold release input p43 : sio1 data output p44 : sio1 data input/bus input/output p45 : sio1 clock input/output p46 : pwm0a output p47 : pwm0boutput interrupt acknowledge type int6, int7 : h level, l level, h edge, l edge, both edges p40 to p47 port 5 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? hold release input ? port 0 interrupt input p50 to p57 port 6 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? pin functions an0 (p60) to an7 (p67) : ad converter input port p60 to p67 port 7 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? pin functions an8 (p70) to an15 (p77) : ad converter input port p70 to p77 continued on next page.
LC88FC3J0A www.onsemi.com 13 continued from preceding page. pin name i/o description port a i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? multiplexed pin functions pa0 : sio4 data output pa1 : sio4 data input/pulse input/output pa2 : sio4 clock input/output pa3 : sio4 chip select input pa4 : sliic0 clock input pa5 : sliic0 bus input/output/data input pa6 : sliic0 data output (used in 3-wire sio mode) pa0 to pa7 port b i/o ? 7-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units ? multiplexed pin functions pb4 : smiic1 clock input/output pb5 : smiic1 bus input/output/data input pb6 : smiic1 data output (used in 3-wire sio mode) pb0 to pb6 port c i/o ? 5-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units(pc2) ? pin functions pc0 : 32.768 khz crystal oscillator input pc1 : 32.768 khz crystal oscillator output pc2 : filt of vco pc3 : ceramic oscillator input pc4 : ceramic oscillator output/vco output pc0 to pc4 port d i/o ? 6-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1 bit units pd0 to pd5 test i/o ? test pin ? used to communicate with on-chip debugger. ? connects an external 100 k ? pull-down resistor. resb i/o reset pin
LC88FC3J0A www.onsemi.com 14 port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of output type pull-up resistor p00 to p07 1 bit cmos programmable p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p77 pa0 to pa7 pb0 to pb6 able to program special functions?output type from cmos output or nch-opendrain p60 to p67 p70 to p77 pd0 to pd5 pc2 cmos pc0 ? n-channel open drain (32.768 khz crysta l oscillator input) none pc1 ? nch-open drain (32.768k khz crys tal oscillator output) none pc3 ? cmos (ceramic oscillator input) none pc4 ? cmos (ceramic oscillator output) none * make the following connection to minimize the noise input to the vdd1 pin and prolong the backup time. be sure to electrically short the vss1, vss2, vss3 and vss4 pins. example 1 : when data is being backed up in the hold mode, the h level signals to the output ports are fed by the backup capacitors. lsi power supply v ss 1 for buckup v ss 2 v ss 3 v dd 3 v dd 2 v dd 1 v dd 4 v ss 4
LC88FC3J0A www.onsemi.com 15 example 2 : when data is being backed up in the hold mode, the h level output at any ports is not sustained and is unpredictable. power supply for buckup v dd 3 v dd 2 v dd 1 lsi v ss 1 v ss 2 v ss 3 v dd 4 v ss 4
LC88FC3J0A www.onsemi.com 16 absolute maximum ratings at ta=25 ? c, v ss 1=v ss 2=v ss 3=v ss 4=0v parameter symbol applicable pin /remarks conditions specification v dd [v] min typ max unit maximum supply voltage v dd max v dd 1, v dd 2, v dd 3, v dd 4 v dd 1=v dd 2=v dd 3 = v dd 4 ? 0.3 +4.6 v input voltage vi (1) resb ? 0.3 v dd +0.3 input/output voltage vio (1) ports 0, 1, 2 ports 3, 4, 5 ports 6, 7 ports a, b, c, d ? 0.3 vdd +0.3 high level output current peak output current ioph (1) ports 0, 1, 2, 3 p40 to p45 ports 7, a, d pb2 to pb6 cmos output selected per applicable pin ? 7.5 ma ioph (2) p46, p47 pb0, pb1 per applicable pin ? 12.5 ioph (3) port 5, 6 pc0 to pc4 per applicable pin ? 4.5 average output current (note 1-1) iomh (1) ports 0, 1, 2, 3 p40 to p45 ports 5, 6, 7, a pb2 to pb6 ports d cmos output selected per applicable pin ? 5 iomh (2) p46, p47 pb0, pb1 per applicable pin ? 10 iomh (3) port 5, 6 pc0 to pc4 per applicable pin ? 3 total output current ? ioah (1) pprts 5 pc0 to pc4 total of currents at applicable pins ? 10 ? ioah (2) port 6 total of currents at applicable pins ? 10 ? ioah (3) port 5, 6 pc0 to pc4 total of currents at applicable pins ? 20 ? ioah (4) ports 1,d1 p20 to p21 total of currents at applicable pins ? 20 ? ioah (5) p22 to p27 total of currents at applicable pins ? 20 ? ioah (6) ports 1, 2, d total of currents at applicable pins ? 40 ? ioah (7) ports 4 total of currents at applicable pins ? 20 ? ioah (8) ports 0, 3 total of currents at applicable pins ? 20 ? ioah (9) ports 0, 3, 4 total of currents at applicable pins ? 40 ? ioah (10) ports b, 7 total of currents at applicable pins ? 20 ? ioah (11) ports a total of currents at applicable pins ? 20 ? ioah (12) ports 7, a, b total of currents at applicable pins ? 40 note 1-1 : average output current refers to the average of output currents measured for a period of 100 ms. continued on next page.
LC88FC3J0A www.onsemi.com 17 continued from preceding page. parameter symbol applicable pin /remarks conditions specification v dd [v] min typ max unit low level output current peak output current iopl (1) ports 0, 1, 3, 4 ports 7, d p20, p21, p24 to p27 pa0 to pa4, pa6, pa7 pb0 to pb4, pb6, per applicable pin 15 ma iopl (2) p22, p23 pa4, pa5 pb4, pb5 per applicable pin 20 iopl (3) ports 5, 6 pc0 to pc4 per applicable pin 7.5 average output current (note 1-1) ioml (1) ports 0, 1, 3, 4 ports 7, d p20, p21, p24 to p27 pa0 to pa4, pa6, pa7 pb0 to pb4, pb6, pb7 per applicable pin 12.5 ioml (2) p22, p23 pa4, pa5 pb4, pb5 per applicable pin 15 ioml (3) ports 5, 6 pc0 to pc4 per applicable pin 5 total output current ? ioal (1) ports 5 pc0 to pc2 total of currents at applicable pins 10 ? ioal (2) port 6 pc3 to pc4 total of currents at applicable pins 10 ? ioal (3) port 5, 6 pc0 to pc4 total of currents at applicable pins 20 ? ioal (4) ports 1, d p20, p21 total of currents at applicable pins 35 ? ioal (5) p22 to p27 total of currents at applicable pins 35 ? ioal (6) ports 1, 2, d total of currents at applicable pins 70 ? ioal (7) port 4 total of currents at applicable pins 35 ? ioal (8) port 0, 3 total of currents at applicable pins 35 ? ioal (9) port 0, 3, 4 total of currents at applicable pins 70 ? ioal (10) port 7, b total of currents at applicable pins 35 ? ioal (11) port a total of currents at applicable pins 35 ? ioal (12) port 7, a, b total of currents at applicable pins 70 allowable power dissipation pd max tqfp100 ta= ? 40 to +85 ? c package with thermal resistance bord (note 1-2) 460 mw operating ambient temperature topr ? 40 +85 ? c storage ambient temperature tstg ? 55 +125 note 1-1 : average output current refers to the average of output currents measured for a period of 100 ms. note 1-2 : semi standerds therma l resistance board (size : 76.1 ? 114.3 ? 1.6 tmm, glass epoxy) is used. stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected.
LC88FC3J0A www.onsemi.com 18 allowable operating conditions at ta=?40 to +85 ? c, v ss 1=v ss 2=v ss 3=v ss 4=0v parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit operating supply voltage v dd (1) v dd 1=v dd 2=v dd 3 0.098 ? s tcyc 66 ? s 2.7 3.6 v memory sustaining supply voltage vhd v dd 1=v dd 2=v dd 3 ram and register contents sustained in hold mode 2.0 3.6 high level input voltage vih (1) ports 0, 1, 2, 3, 4 port 5, a, b 2.7 to 3.6 0.3v dd +0.7 v dd vih (2) ports 6, 7, d,pc2 2.7 to 3.6 0.3v dd +0.7 v dd vih (3) resb pc0, pc1, pc3, pc4 2.7 to 3.6 0.75v dd v dd vih (4) p22, p23, pa4, pa5, pb4, pb5 i2c side 2.7 to 3.6 0.7v dd v dd low level input voltage vil (1) when ports 1, 2, 3, 4, 5, a and port b, pnfsan=0 ports 0, 6, 7, d, pc2 2.7 to 3.6 v ss 0.2v dd vil (2) when ports 1, 2, 3, 4, 5, a and port b, pnfsan=1 2.7 to 3.6 v ss 0.2v dd vil (3) cf1, resb pc0, pc1,pc3, pc4 2.7 to 3.6 v ss 0.25v dd vil (4) p22, p23, pa4, pa5, pb4, pb5 i2c side 2.7 to 3.6 v ss 0.3v dd instruction cycle time (note 2-1) tcyc 2.7 to 3.6 0.098 66 ? s external system clock frequency fexcf (1) cf1 ? cf2 pin open ? system clock frequency division ratio = 1/1 ? external system clock duty50 ? 5% 2.7 to 3.6 0.1 10 mhz ? cf2 pin open ? system clock frequency division ratio = 1/2 2.7 to 3.6 0.2 20 note 2-1 : relationship between tcyc and oscillation fre quency is 1/fmcf when frequency division ratio is 1/1 and 2/fmcf when the ratio is 1/2. continued on next page.
LC88FC3J0A www.onsemi.com 19 continued from preceding page. parameter symbol applicable pin /remarks conditions specification v dd [v] min typ max unit oscillation frequency range (note 2-2) fmcf pc3(cf1), pc4(cf2) 10 mhz ceramic oscillator mode see fig. 1. 2.7 to 3.6 10 mhz fmrc internal rc oscillation 2.7 to 3.6 0.5 1.0 2.0 fmslrc internal low-speed rc oscillation 2.7 to 3.6 18 30 45 khz fsx'tal xt1, xt2 32.768 khz crystal oscillator mode see fig. 2. 2.7 to 3.6 32.768 fmvco(1) vco oscillator when setting frqsel=0 see fig. 9. 2.7 to 3.6 12 28 mhz fmvco(2) vco oscillator when setting frqsel=1 see fig. 9. 2.7 to 3.6 38 70 fmvco(5) vco oscillator 2.7 to 3.6 note 2-3 note 2-2 : see tables 1 and 2 for oscillator constant values. note 2-3 : vco oscillation frequency = c eramic oscillator frequency ? setting point of selref functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility.
LC88FC3J0A www.onsemi.com 20 electrical characteristics at ta=?40 to +85 ? c, v ss 1=v ss 2=v ss 3=v ss 4=0v parameter symbol applicable pin /remarks conditions specification v dd [v] min typ max unit high level input current iih (1) ports 0, 1, 2 ports 3, 4, 5 ports 6, 7 ports a, b,c, d resb output disabled pull-up resistor off v in =v dd (including output tr. off leakage current) 2.7 to 3.6 1 ? a low level input current iil (1) ports 0, 1, 2 ports 3, 4, 5 ports 6, 7 ports a, b, c, d resb output disabled pull-up resistor off v in =v ss (including output tr. off leakage current) 2.7 to 3.6 ? 1 high level output voltage voh (1) ports 0, 1, 2, 3 ports 5, 6 ports a, d, pc2 p40 to p45 pb2 to pb6 ioh= ? 0.4ma 3.0 to 3.6 v dd ? 0.4 v voh (2) ioh= ? 0.2ma 2.7 to 3.6 v dd ? 0.4 voh (3) p46, p47 pb0, pb1 ioh= ? 1.6ma 3.0 to 3.6 v dd ? 0.4 voh (4) ioh= ? 1.0ma 2.7 to 3.6 v dd ? 0.4 voh (5) pc0, pc1, pc3, pc4, ioh= ? 1.0ma 3.0 to 3.6 v dd ? 0.4 voh (6) ioh= ? 0.4ma 2.7 to 3.6 v dd ? 0.4 low level output voltage vol (1) ports 0, 1, 3 , 4 ports 5, 6, 7, d pc2 p20 to p21, p24 to p27 pa0 to pa3 pa6 to pa7 pb0 to pb3, pb6 iol=1.6ma 3.0 to 3.6 0.4 vol (2) iol=1.0ma 2.7 to 3.6 0.4 vol (3) p22, p23, pa4, pa5, pb4, pb5 iol=3.0ma 3.0 to 3.6 0.4 vol (4) iol=1.3ma 2.7 to 3.6 0.4 vol (5) pc0, pc1, pc3, pc4, iol=1.0ma 3.0 to 3.6 0.4 vol (6) iol=0.4ma 2.7 to 3.6 0.4 pull-up resistor rpu (1) ports 0, 1, 2, 3 ports 4, 5, 6, 7 ports a, b, d, pc2 voh=0.9v dd 3.0 to 3.6 15 35 80 k ? rpu (2) 2.7 to 3.6 15 35 100 hysteresis voltage vhys resb when ports 1, 2, 3, 4, a, b pnfsan=1 2.7 to 3.6 0.1v dd v pin capacitance cp all pins pins other than that under test v in =v ss f=1 mhz ta=25 ? c 2.7 to 3.6 10 pf product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions.
LC88FC3J0A www.onsemi.com 21 serial i/o characteristics at ta=?40 to +85 ? c, v ss 1=v ss 2=v ss 3=v ss 4=0v serial i/o characteristics (wakeup function disabled) (note 4-1-1) parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit serial clock input clock period tsck (1) sck0 (p12) ? see fig. 6. 2.7 to 3.6 4 tcyc low level pulse width tsckl (1) 2 high level pulse width tsckh (1) 2 tsckha (1) ? automatic communication mode ? see fig. 6. 6 tsckhbsy (1a) ? automatic communication mode ? see fig. 6. 23 tsckhbsy (1b) ? mode other than automatic communication mode ? see fig. 6. 4 output clock period tsck (2) sck0 (p12) ? cmos output selected ? see fig. 6. 2.7 to 3.6 4 low level pulse width tsckl (2) 1/2 tsck high level pulse width tsckh (2) 1/2 tsckha (2) ? automatic communication mode ? cmos output selected ? see fig. 6. 6 tcyc tsckhbsy (2a) ? automatic communication mode ? cmos output selected ? see fig. 6. 4 23 tsckhbsy (2b) ? mode other than automatic communication mode ? see fig. 6. 4 serial input data setup time tsdi (1) si0 (p11), sb0 (p11) ? specified with respect to rising edge of sioclk ? see fig. 6. 2.7 to 3.6 0.03 ? s data hold time thdi (1) 0.03 serial output input clock output delay time tdd0 (1) so0 (p10), sb0 (p11) ? (note 4-1-2) 2.7 to 3.6 1tcyc +0.05 output clock tddo (2) ? (note 4-1-2) 1tcyc +0.05 note 4-1-1 : these specifications are theoretical values. add margin depending on its use. note 4-1-2 : specified with respect to the falling edge of sioclk. specified as the in terval up to the time an output change begins in the open drain output mode. see fig. 6.
LC88FC3J0A www.onsemi.com 22 sio0 serial input/output characteristi cs (wakeup function enabled) (note 4-2-1) parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit serial clock input clock period tsck (3) sck0 (p12) ? see fig. 6. 2.7 to 3.6 2 tcyc low level pulse width tsckl (3) 1 high level pulse width tsckh (3) 1 tsckhbsy (3) 2 serial input data setup time tsdi (2) si0 (p11), sb0 (p11) ? specified with respect to rising edge of sioclk ? see fig. 6. 2.7 to 3.6 0.03 ? s data hold time thdi (2) 0.03 serial output input clock output delay time tdd0 (3) so0 (p10), sb0 (p11) ? (note 4-2-2) 2.7 to 3.6 1tcyc +0.05 note 4-2-1 : these specifications are theoretical values. add margin depending on its use. note 4-2-2 : specified with respect to the falling edge of sioclk. specified as the in terval up to the time an output change begins in the open drain output mode. see fig. 6.
LC88FC3J0A www.onsemi.com 23 sio1 serial input/output characteristi cs (wakeup function disabled) (note 4-3-1) parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit serial clock input clock period tsck (4) sck1 (p45) ? see fig. 6. 2.7 to 3.6 4 tcyc low level pulse width tsckl (4) 2 high level pulse width tsckh (4) 2 tsckha (4) ? automatic communication mode ? see fig. 6. 6 tsckhbsy (4a) ? automatic communication mode ? see fig. 6. 23 tsckhbsy (4b) ? mode other than automatic communication mode ? see fig. 6. 4 output clock period tsck (5) sck1 (p45) ? cmos output selected ? see fig. 6. 2.7 to 3.6 4 low level pulse width tsckl (5) 1/2 tsck high level pulse width tsckh (5) 1/2 tsckha (5) ? automatic communication mode ? cmos output selected ? see fig. 6. 6 tcyc tsckhbsy (5a) ? automatic communication mode ? cmos output selected ? see fig. 6. 4 23 tsckhbsy (5b) ? mode other than automatic communication mode ? see fig. 6. 4 serial input data setup time tsdi (3) si1 (p44), sb1 (p44) ? specified with respect to rising edge of sioclk ? see fig. 6. 2.7 to 3.6 0.03 ? s data hold time thdi (3) 0.03 serial output input clock output delay time tdd0 (4) so1 (p43), sb1 (p44) ? (note 4-3-2) 2.7 to 3.6 1tcyc +0.05 output clock tddo (5) ? (note 4-3-2) 1tcyc +0.05 note 4-3-1 : these specifications are theoretical values. add margin depending on its use. note 4-3-2 : specified with respect to the falling edge of sioclk. specified as the in terval up to the time an output change begins in the open drain output mode. see fig. 6.
LC88FC3J0A www.onsemi.com 24 sio1 serial input/output characteristi cs (wakeup function enabled) (note 4-4-1) parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit serial clock input clock period tsck (6) sck1 (p45) ? see fig. 6. 2.7 to 3.6 2 tcyc low level pulse width tsckl (6) 1 high level pulse width tsckh (6) 1 tsckhbsy (6) 2 serial input data setup time tsdi (4) si1 (p44), sb1 (p44) ? specified with respect to rising edge of sioclk ? see fig. 6. 2.7 to 3.6 0.03 ? s data hold time thdi (4) 0.03 serial output input clock output delay time tdd0 (6) so1 (p43), sb1 (p44) ? (note 4-4-2) 2.7 to 3.6 1tcyc +0.05 note 4-4-1 : these specifications are theoretical values. add margin depending on its use. note 4-4-2 : specified with respect to the falling edge of sioclk. specified as the in terval up to the time an output change begins in the open drain output mode. see fig. 6.
LC88FC3J0A www.onsemi.com 25 sio4 serial input/output characteristi cs (wakeup function disabled) (note 4-5-1) parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit serial clock input clock period tsck (7) sck4 (pa2) ? see fig. 6. 2.7 to 3.6 4 tcyc low level pulse width tsckl (7) 2 high level pulse width tsckh (7) 2 tsckha (7) ? automatic communication mode ? see fig. 6. 6 tsckhbsy (7a) ? automatic communication mode ? see fig. 6. 23 tsckhbsy (7b) ? mode other than automatic communication mode ? see fig. 6. 4 output clock period tsck (8) sck4 (pa2) ? cmos output selected ? see fig. 6. 2.7 to 3.6 4 low level pulse width tsckl (8) 1/2 tsck high level pulse width tsckh (8) 1/2 tsckha (8) ? automatic communication mode ? cmos output selected ? see fig. 6. 6 tcyc tsckhbsy (8a) ? automatic communication mode ? cmos output selected ? see fig. 6. 4 23 tsckhbsy (8b) ? mode other than automatic communication mode ? see fig. 6. 4 serial input data setup time tsdi (5) si4 (pa1), sb4 (pa1) ? specified with respect to rising edge of sioclk ? see fig. 6. 2.7 to 3.6 0.03 ? s data hold time thdi (5) 0.03 serial output input clock output delay time tdd0 (7) so4 (pa0), sb14(pa1) ? (note 4-5-2) 2.7 to 3.6 1tcyc +0.05 output clock tddo (8) ? (note 4-5-2) 1tcyc +0.05 note 4-5-1 : these specifications are theoretical values. add margin depending on its use. note 4-5-2 : specified with respect to the falling edge of sioclk. specified as the in terval up to the time an output change begins in the open drain output mode. see fig. 6.
LC88FC3J0A www.onsemi.com 26 sio4 serial input/output characteristi cs (wakeup function enabled) (note 4-6-1) parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit serial clock input clock period tsck (9) sck4 (p45) ? see fig. 6. 2.7 to 3.6 2 tcyc low level pulse width tsckl (9) 1 high level pulse width tsckh (9) 1 tsckhbsy (9) 2 serial input data setup time tsdi (6) si4 (p44), sb4 (p44) ? specified with respect to rising edge of sioclk ? see fig. 6. 2.7 to 3.6 0.03 ? s data hold time thdi (6) 0.03 serial output input clock output delay time tdd0 (9) so4 (p43), sb4(p44) ? (note 4-6-2) 2.7 to 3.6 1tcyc +0.05 note 4-6-1 : these specifications are theoretical values. add margin depending on its use. note 4-6-2 : specified with respect to the falling edge of sioclk. specified as the in terval up to the time an output change begins in the open drain output mode. see fig. 6.
LC88FC3J0A www.onsemi.com 27 smiic0 simple sio mode input/output characteristics (note 4-7-1) parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit serial clock input clock period tsck (10) sm0ck (p22) see fig. 6. 2.7 to 3.6 4 tcyc low level pulse width tsckl (10) 2 high level pulse width tsckh (10) 2 output clock period tsck (11) sm0ck (p22) ? cmos output selected ? see fig. 6. 2.7 to 3.6 4 low level pulse width tsckl (11) 1/2 tsck high level pulse width tsckh (11) 1/2 serial input data setup time tsdi (7) sm0da (p23), ? specified with respect to rising edge of sioclk ? see fig. 6. 2.7 to 3.6 0.03 ? s data hold time thdi (7) 0.03 serial output output delay time tdd0 (10) sm0do (p24), sm0da (p23) ? specified with respect to falling edge of sioclk ? specified as interval up to time when output state starts changing. ? see fig. 6. 2.7 to 3.6 1tcyc +0.05 note 4-7-1 : these specifications are theoretical values. add margin depending on its use.
LC88FC3J0A www.onsemi.com 28 smiic0 i 2 c mode input/output characteristics (not e 4-8-1) (note 4-8-2) (note 4-8-4) parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit clock input clock period tscl sm0ck (p22) ? see fig. 8. 2.7 to 3.6 5 tfilt low level pulse width tscll 2.5 high level pulse width tsclh 2 output clock period tsclx sm0ck (p22) ? specified as interval up to time when output state starts changing. 2.7 to 3.6 10 low level pulse width tscllx 1/2 tscl high level pulse width tsclhx 1/2 sm0ck and sm0da pins input spike suppression time tsp sm0ck (p22) sm0da (p23) ? see fig. 8. 2.7 to 3.6 1 tfilt bus release time between start and stop input tbuf sm0ck (p22) sm0da (p23) ? see fig. 8. 2.7 to 3.6 2.5 tfilt output tbufx sm0ck (p22) sm0da (p23) ? standard clock mode ? specified as interval up to time when output state starts changing. 5.5 s ? high-speed clock mode ? specified as interval up to time when output state starts changing. 1.6 start/restart condition hold time input thd;sta sm0ck (p22) sm0da (p23) ? when smiic register control bit, i2cshds=0 ? see fig. 8. 2.7 to 3.6 2.0 tfilt ? when smiic register control bit i2cshds=1 ? see fig. 8. 2.5 output thd;stax sm0ck (p22) sm0da (p23) ? standard clock mode ? specified as interval up to time when output state starts changing. 4.1 s ? high-speed clock mode ? specified as interval up to time when output state starts changing. 1.0 restart condition setup time input tsu;sta sm0ck (p22) sm0da (p23) ? see fig. 8. 2.7 to 3.6 1.0 tfilt output tsu;stax sm0ck (p22) sm0da (p23) ? standard clock mode ? specified as interval up to time when output state starts changing. 5.5 s ? high-speed clock mode ? specified as interval up to time when output state starts changing. 1.6
LC88FC3J0A www.onsemi.com 29 parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit stop condition setup time input tsu;sto sm0ck (p22) sm0da (p23) ? see fig. 8. 2.7 to 3.6 1.0 tfilt output tsu;stox sm0ck (p22) sm0da (p23) ? standard clock mode ? specified as interval up to time when output state starts changing. 4.9 ? s ? high-speed clock mode ? specified as interval up to time when output state starts changing. 1.1 data hold time input thd;dat sm0ck (p22) sm0da (p23) ? see fig. 8. 2.7 to 3.6 0 tfilt output thd;datx sm0ck (p22) sm0da (p23) ? specified as interval up to time when output state starts changing. 1 1.5 data setup time input tsu;dat sm0ck (p22) sm0da (p23) ? see fig. 8. 2.7 to 3.6 1 tfilt output tsu;datx sm0ck (p22) sm0da (p23) ? specified as interval up to time when output state starts changing. 1tscl- 1.5tfilt sm0ck and sm0da pins fall time input tf sm0ck (p22) sm0da (p23) ? see fig. 8. 2.7 to 3.6 300 ns output tf sm0ck (p22) sm0da (p23) ? when smiic register control bits pslw=1, p5v=1 3 20+0.1cb (note 4-8-3) 250 ? sm0ck, sm0da port output fast mode ? cb 100pf 3.0 to 3.6 100 note 4-8-1 : these specifications are theoretical values. add margin depending on its use. note 4-8-2 : the value of tfilt is determined by the va lues of the register smic0brg, bits 7 and 6 (brp1, brp0) and the system clock frequency. brp1 brp0 tfilt 0 0 tcyc ? 1 0 1 tcyc ? 2 1 0 tcyc ? 3 1 1 tcyc ? 4 set bits (bpr1, bpr0) so that the value of tfilt falls between the following range : 250 ns tfilt > 140 ns note 4-8-3: cb represents the total loads (in pf) connected to the bus pins. cb 100 pf note 4-8-4: the standard clock mode refers to a mode that is entered by configuring smic0brg as follows : 250 ns tfilt > 140 ns brdq (bit5) = 1 scl frequency setting 100 khz the high-speed clock mode refers to a mode that is entered by configuring smic0brg as follows : 250 ns tfilt > 140 ns brdq (bit5) = 0 scl frequency setting 400 khz
LC88FC3J0A www.onsemi.com 30 smiic1 simple sio mode input/output characteristics (note 4-9-1) parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit serial clock input clock period tsck (12) sm0ck (pb4) see fig. 6. 2.7 to 3.6 4 tcyc low level pulse width tsckl (12) 2 high level pulse width tsckh (12) 2 output clock period tsck (13) sm0ck (pb4) ? cmos output selected ? see fig. 6. 2.7 to 3.6 4 low level pulse width tsckl (13) 1/2 tsck high level pulse width tsckh (13) 1/2 serial input data setup time tsdi (8) sm0da (pb5), ? specified with respect to rising edge of sioclk ? see fig. 6. 2.7 to 3.6 0.03 ? s data hold time thdi (8) 0.03 serial output output delay time tdd0 (12) sm0do (pb6), sm0da (pb5) ? specified with respect to falling edge of sioclk ? specified as interval up to time when output state starts changing. ? see fig. 6. 2.7 to 3.6 1tcyc +0.05 note 4-9-1 : these specifications are theoretical values. add margin depending on its use.
LC88FC3J0A www.onsemi.com 31 smiic1 i 2 c mode input/output characteristics (note 4-10-1) (note 4-10-2) (note 4-10-4) parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit clock input clock period tscl sm1ck (pb4) ? see fig. 8. 2.7 to 3.6 5 tfilt low level pulse width tscll 2.5 high level pulse width tsclh 2 output clock period tsclx sm1ck (pb4) ? specified as interval up to time when output state starts changing. 2.7 to 3.6 10 low level pulse width tscllx 1/2 tscl high level pulse width tsclhx 1/2 sm0ck and sm0da pins input spike suppression time tsp sm1ck (pb4) sm1da (pb5) ? see fig. 8. 2.7 to 3.6 1 tfilt bus release time between start and stop input tbuf sm1ck (pb4) sm1da (pb5) ? see fig. 8. 2.7 to 3.6 2.5 tfilt output tbufx sm1ck (pb4) sm1da (pb5) ? standard clock mode ? specified as interval up to time when output state starts changing. 5.5 sec ? high-speed clock mode ? specified as interval up to time when output state starts changing. 1.6 start/restart condition hold time input thd;sta sm1ck (pb4) sm1da (pb5) ? when smiic register control bit, i2cshds=0 ? see fig. 8. 2.7 to 3.6 2.0 tfilt ? when smiic register control bit i2cshds=1 ? see fig. 8. 2.5 output thd;stax sm1ck (pb4) sm1da (pb5) ? standard clock mode ? specified as interval up to time when output state starts changing. 4.1 sec ? high-speed clock mode ? specified as interval up to time when output state starts changing. 1.0 restart condition setup time input tsu;sta sm1ck (pb4) sm1da (pb5) ? see fig. 8. 2.7 to 3.6 1.0 tfilt output tsu;stax sm1ck (pb4) sm1da (pb5) ? standard clock mode ? specified as interval up to time when output state starts changing. 5.5 sec ? high-speed clock mode ? specified as interval up to time when output state starts changing. 1.6
LC88FC3J0A www.onsemi.com 32 parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit stop condition setup time input tsu;sto sm1ck (pb4) sm1da (pb5) ? see fig. 8. 2.7 to 3.6 1.0 tfilt output tsu;stox sm1ck (pb4) sm1da (pb5) ? standard clock mode ? specified as interval up to time when output state starts changing. 4.9 ? sec ? high-speed clock mode ? specified as interval up to time when output state starts changing. 1.1 data hold time input thd;dat sm1ck (pb4) sm1da (pb5) ? see fig. 8. 2.7 to 3.6 0 tfilt output thd;datx sm1ck (pb4) sm1da (pb5) ? specified as interval up to time when output state starts changing. 1 1.5 data setup time input tsu;dat sm1ck (pb4) sm1da (pb5) ? see fig. 8. 2.7 to 3.6 1 tfilt output tsu;datx sm1ck (pb4) sm1da (pb5) ? specified as interval up to time when output state starts changing. 1tscl-1.5tfilt sm0ck and sm0da pins fall time input tf sm1ck (pb4) sm1da (pb5) ? see fig. 8. 2.7 to 3.6 300 ns output tf sm1ck (pb4) sm1da (pb5) ? when smiic register control bits pslw=1, phv=1 3 20+0.1cb (note 4-10-3) 250 ? sm0ck, sm0da port output fast mode ? cb 100pf 3 to 3.6 100 note 4-10-1 : these sp ecifications are theoretical values. add margin depending on its use. note 4-10-2 : the value of tfilt is determined by the values of the register smic1brg, bits 7 and 6 (brp1, brp0) and the system clock frequency. brp1 brp0 tfilt 0 0 tcyc ? 1 0 1 tcyc ? 2 1 0 tcyc ? 3 1 1 tcyc ? 4 set bits (bpr1, bpr0) so that the value of tfilt falls between the following range : 250 ns tfilt > 140 ns note 4-10-3 : cb represents the total loads (in pf) connected to the bus pins. cb 100 pf note 4-10-4 : the standard clock mode refers to a mode that is entered by configuring smic0brg as follows : 250 ns tfilt > 140 ns brdq (bit5) = 1 scl frequency setting 100 khz the high-speed clock mode refers to a mode that is entered by configuring smic1brg as follows : 250 ns tfilt > 140 ns brdq (bit5) = 0 scl frequency setting 400 khz
LC88FC3J0A www.onsemi.com 33 sliic0 simple sio mode input/output characteristics (note 4-11-1) parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit serial clock input clock period tsck (13) sl0ck (pa4) see fig. 6. 2.7 to 3.6 4 tcyc low level pulse width tsckl (13) 2 high level pulse width tsckh (13) 2 serial input data setup time tsdi (9) sl0da (pa5), ? specified with respect to rising edge of sioclk ? see fig. 6. 2.7 to 3.6 0.03 ? s data hold time thdi (9) 0.03 serial output output delay time tdd0 (13) sl0do (pa6), sl0da (pa5) ? specified with respect to falling edge of sioclk ? specified as interval up to time when output state starts changing. ? see fig. 6. 2.7 to 3.6 1tcyc +0.05 note 4-11-1 : these sp ecifications are theoretical values. add margin depending on its use.
LC88FC3J0A www.onsemi.com 34 sliic1 i 2 c mode input/output characteristics (note 4-12-1) (note 4-12-2) parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit clock input clock period tscl sl0ck (pa4) ? see fig. 8. 2.7 to 3.6 5 tfilt low level pulse width tscll 2.5 high level pulse width tsclh 2 sl0ck and sl0da pins input spike suppression time tsp sl0ck (pa4) sl0da (pa5) ? see fig. 8. 2.7 to 3.6 1 tfilt bus release time between start and stop input tbuf sl0ck (pa4) sl0da (pa5) ? see fig. 8. 2.7 to 3.6 2.5 tfilt start/restart condition hold time input thd;sta sl0ck (pa4) sl0da (pa5) ? when smiic register control bit, i2cshds=0 ? see fig. 8. 2.7 to 3.6 2.0 tfilt ? when smiic register control bit i2cshds=1 ? see fig. 8. 2.5 restart condition setup time input tsu;sta sl0ck (pa4) sl0da (pa5) ? see fig. 8. 2.7 to 3.6 1.0 tfilt stop condition setup time in p ut tsu;sto sl0ck (pa4) sl0da (pa5) ? see fig. 8. 2.7 to 3.6 1.0 tfilt data hold time in p ut thd;dat sl0ck (pa4) sl0da (pa5) ? see fig. 8. 2.7 to 3.6 0 tfilt out p ut thd;datx sl0ck (pa4) sl0da (pa5) ? specified as interval up to time when output state starts changing. 1 1.5 data setup time in p ut tsu;dat sl0ck (pa4) sl0da (pa5) ? see fig. 8. 2.7 to 3.6 1 tfilt out p ut tsu;datx sl0ck (pa4) sl0da (pa5) ? specified as interval up to time when output state starts changing. 1tscl- 1.5tfilt
LC88FC3J0A www.onsemi.com 35 parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit sl0ck and sl0da pins fall time input tf sl0ck (pa4) sl0da (pa5) ? see fig. 8. 2.7 to 3.6 300 ns output tf sl0ck (pa4) sl0da (pa5) ? when sliic0 register control bits pslw=1, phv=1 3 20+0.1cb (note 4-12-3) 250 ? sl0ck, sl0da port output fast mode ? cb 100pf 3.0 to 3.6 100 note 4-12-1 : these sp ecifications are theoretical values. add margin depending on its use. note 4-12-2 : the value of tfilt is determined by the va lues of the register slic0p cnt, bits 5 and 4 (brp1, brp0) and the system clock frequency. brp1 brp0 tfilt 0 0 tcyc ? 1 0 1 tcyc ? 2 1 0 tcyc ? 3 1 1 tcyc ? 4 set bits (bpr1, bpr0) so that the value of tfilt falls between the following range : 250 ns tfilt > 140 ns note 4-12-3: cb represents the total loads (in pf) connected to the bus pins. cb 100 pf
LC88FC3J0A www.onsemi.com 36 uart0 operating conditions at ta=?40 to +85 ? c, v ss 1=v ss 2=v ss 3=v ss 4=0v parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit transfer rate ubr0 u0rx (p13), u0tx (p14), u0brg (p07) 2.7 to 3.6 4 8 tbgcyc note 4-9 : tbgcyc denotes one cy cle of the baudrate clock source. uart2 operating conditions at ta=?40 to +85 ? c, v ss 1=v ss 2=v ss 3=v ss 4=0v parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit transfer rate ubr2 u2rx (p16), u2tx (p17), 2.7 to 3.6 8 4096 tbgcyc note 4-10: tbgcyc denotes one cy cle of the baudrate clock source. uart3 operating conditions at ta=?40 to +85 ? c, v ss 1=v ss 2=v ss 3=v ss 4=0v parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit transfer rate ubr3 u3rx (p34), u3tx (p35), 2.7 to 3.6 8 4096 tbgcyc note 4-10 : tbgcyc denotes one cy cle of the baudrate clock source. pulse input conditions at ta=?40 to +85 ? c, v ss 1=v ss 2=v ss 3=v ss 4=0v parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit high/low level pulse width tpih (1) tpil (1) int0 (p30), int1 (p31), int2 (p32), int3 (p33), int4 (p20), int5 (p21), int6 (p40), int7 (p41) ? interrupt source flag can be set. ? event inputs for timers 2 and 3 are enabled. 2.7 to 3.6 2 tcyc tpil (2) resb resetting is enabled. 2.7 to 3.6 10 ? s
LC88FC3J0A www.onsemi.com 37 ad converter characteristics at ta=?40 to +85 ? c, v ss 1=v ss 2=v ss 3=v ss 4=0v 12-bit ad conversion mode parameter symbol applicable pin /remarks conditions specification v dd [v] min typ max unit resolution nad an0 (p60) to an7 (p67), an8 (p70) to an15 (p77) 2.7 to 3.6 12 bit absolute accuracy etad (note 6-1) 2.7 to 3.6 ? 16 lsb conversion time tcad12 conversion time calculated 3.0 to 3.6 64 115 ? s 2.7 to 3.6 128 230 analog input voltage range vain 2.7 to 3.6 v ss v dd v analog port input current iainh vain=v dd 2.7 to 3.6 1 ? a iainl vain=v ss 2.7 to 3.6 ? 1 ? conversion time calculation formula : tcad12 = ( ratio division ad 52 +2) ? tcyc 8-bit ad conversion mode parameter symbol applicable pin /remarks conditions specification v dd [v] min typ max unit resolution nad an0 (p60) to an7 (p67), an8 (p70) to an15 (p77) 2.7 to 3.6 8 bit absolute accuracy etad (note 6-1) 2.7 to 3.6 ? 1.5 lsb conversion time tcad8 conversion time calculated 3.0 to 3.6 39 71 ? s 2.7 to 3.6 79 140 analog input voltage range vain 2.7 to 3.6 v ss v dd v analog port input current iainh vain=v dd 2.7 to 3.6 1 ? a iainl vain=v ss 2.7 to 3.6 ? 1 ? conversion time calculation formula : tcad8 = ( ratio division ad 52 +2) ? tcyc note 6-1 : the quantization error (1/2lsb ) is excluded from th e absolute accuracy. note 6-2 : the conversion time refers to the interval fr om the time a conversion starting instruction is issued till the time the complete digital value against the analog input value is loaded in the result register. the conversion time is twice the normal value when one of the following conditions occurs: - the first ad conversion is executed in the 12 -bit ad conversion mode after a system reset. - the first ad conversion is executed after the ad conversion mode is switched from 8-bit to 12-bit ad conversion mode.
LC88FC3J0A www.onsemi.com 38 consumption current characteristics at ta=?40 to +85 ? c, v ss 1=v ss 2=v ss 3=v ss 4=0v typ : 3.3v parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit normal mode consumption current (note 7-1) iddop (1) v dd 1 =v dd 2 =v dd 3 =v dd 4 ? fmcf=10 mhz ceramic oscillator mode ? fmx'tal=32.768 khz crystal oscillator mode ? system clock set to 10 mhz ? internal rc oscillation stopped ? 1/1 frequency division mode 2.7 to 3.6 5.0 12.0 ma iddop (2) ? fmcf=0hz (oscillation stopped) ? fmx'tal=32.768 khz crystal oscillator mode ? system clock set to internal rc oscillation ? 1/1 frequency division mode 2.7 to 3.6 0.8 2.1 iddop (3) ? fmcf=0hz (oscillation stopped) ? fmx'tal=32.768 khz crystal oscillator mode ? system clock set to 32.768 khz ? internal rc oscillation stopped ? 1/1 frequency division mode 2.7 to 3.6 30 136 ? a continued on next page.
LC88FC3J0A www.onsemi.com 39 continued from preceding page. parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit halt mode consumption current (note 7-1) iddhalt (1) v dd 1 =v dd 2 =v dd 3 =v dd 4 ? halt mode ? fmcf=10 mhz ceramic oscillator mode ? fmx'tal=32.768 khz crystal oscillator mode ? system clock set to 10 mhz ? internal rc oscillation stopped ? 1/1 frequency division mode 2.7 to 3.6 1.5 3.2 ma iddhalt (2) ? halt mode ? fmcf=0hz (oscillation stopped) ? fmx'tal=32.768 khz crystal oscillator mode ? system clock set to internal rc oscillation ? 1/1 frequency division mode 2.7 to 3.6 0.2 0.8 iddhalt (3) ? halt mode ? fmcf=0hz (oscillation stopped) ? fmx'tal=32.768 khz crystal oscillator mode ? system clock set to 32.768 khz ? internal rc oscillation stopped ? 1/1 frequency division mode 2.7 to 3.6 8.5 78 ? a continued on next page.
LC88FC3J0A www.onsemi.com 40 continued from preceding page. parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit hold mode consumption current iddhold (1) v dd 1 hold mode ? cf1=vdd or open (external clock mode) 2.7 to 3.6 0.2 50 ? a iddhold (2) hold mode ? cf1=vdd or open (external clock mode) ? lvd option selected 2.7 to 3.6 1.2 53 holdx mode consumption current iddhold (3) holdx mode ? cf1=vdd or open (external clock mode) ? fmx'tal=32.768 khz crystal oscillator mode 2.7 to 3.6 4.6 71 iddhold (4) holdx mode ? cf1=vdd or open (external clock mode) ? fmx'tal=32.768 khz crystal oscillator mode ? lvd option selected 2.7 to 3.6 5.6 74 note 7-1 : the consumption current value includes none of the currents that flow into the output transistor and internal pull-up resistors. f-rom programming characteristics at ta=+10 to +55 ? c, v ss 1=v ss 2=v ss 3=v ss 4=0v parameter symbol applicable pin/remarks conditions specification v dd [v] min typ max unit onboard programming current iddfw (1) v dd 1 ? microcontroller erase current current is excluded. 2.7 to 3.6 10 ma onboard programming time tfw (1) ? 2k-byte erase operation 2.7 to 3.6 25 ms tfw (2) ? 2-byte programming operation 2.7 to 3.6 45 s
LC88FC3J0A www.onsemi.com 41 power-on reset (por) characteristics at ta= ? 40 to +85 ? c, v ss 1=v ss 2=v ss 3=v ss 4=0v parameter symbol pin/remarks conditions specification option selected voltage min typ max unit por release voltage porrl ? select from option. (note 8-1) 2.57v 2.47 2.57 2.72 v 2.87v 2.77 2.87 3.02 detction voltage unknown state pouks ? see fig 10. (note 8-2) 0.7 0.95 power supply rise time poris ? power supply rise time from 0v to 1.6v. 100 ms note8-1 : the por release level can be selected out of 2 levels only when the lvd reset function is disabled. note8-2 : por is in an unknown state before transistors start operation. low voltage detection reset (lvd) characteristics at ta= ? 40 to +85 ? c, v ss 1=v ss 2=v ss 3=v ss 4=0v parameter symbol pin/remarks conditions specification option selected voltage min typ max unit lvd reset voltage (note 9-1) lvdet ? select from option. (note 9-2) ? see fig 11. 2.81v 2.71 2.81 2.96 v lvd hysteresis width lvhys 2.81v 60 mv detection voltage unknown state lvuks ? see fig 11. (note 9-3) 0.7 0.95 v low voltage detection minimum width (replay sensitivity) tlvdw ? lvdet-0.5v ? see fig 12. 0.2 ms note9-1 : lvd reset voltage specification values do not include hysteresis voltage. note9-2 : lvd reset voltage may exceed its specification va lues when port output state changes and/or when a large current flows through port. note9-3 : lvd is in an unknown state before transistors start operation.
LC88FC3J0A www.onsemi.com 42 power pin treatment conditions 1 (v dd 1, v ss 1) connect capacitors that meet the following conditions between the v dd 1 and v ss 1 pins : - connect among the v dd 1 and v ss 1 pins and the capacitors c1 and c2 w ith the shortest possible lead wires, of the same length (l1=l1', l2=l2') wherever possible. - connect a large-capacity capacitor c1 and a small-capacity capacitor c2 in parallel. the capacitance of c2 should be approximately 0.1 ? f or larger. - the v dd 1 and v ss 1 traces must be thicker than the other traces. power pin treatment conditions 2 (v dd 2, 3, 4 and v ss 2, 3, 4) connect capacitors that meet the following condition between the v dd 2, 3, 4 and v ss 2, 3, 4 pins : - connect among the v dd 2, 3, 4 and v ss 2, 3, 4 pins and the capacitor c3 with the shortest possible lead wires, of the same length (l3=l3') wherever possible. - the capacitance of c3 should be approximately 0.1 ? f or larger. - the v dd 2, 3, 4 and v ss 2, 3, 4 traces must be thicker than the other traces. v ss 1 v dd 1 l1? l2? l1 l2 c1 c2 v ss 2,3, 4 v dd 2,3, 4 l3? l3 c3
LC88FC3J0A www.onsemi.com 43 characteristics of a sample main system clock oscillation circuit given below are the characteristics of a sample main syst em clock oscillation circuit that are measured using a our company -designated oscillation characteristics ev aluation board and external components with circuit constant values with which the oscillator vend or confirmed normal and stable oscillation. table 1 characteristics of a sample main system clock oscillator circuit with a ceramic resonator nominal frequency vendor name resonator circuit constant operating voltage range [v] oscillation stabilization time remarks c3 [pf] c4 [pf] rf [ ? ] rd2 [ ? ] typ [ms] max [ms] 10 mhz murata cstce10m0g52-r0 (10) (10) open 680 2.2 to 2.6 0.02 0.2 c1, c2 integrated type cstls10m0g53-b0 (15) (15) open 680 2.2 to 3.6 0.02 0.2 c1, c2 integrated type the oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after v dd goes above the lower limit level of the operating voltage range (see figure 4) characteristics of a sample s ubsystem clock oscillator circuit given below are the characteristics of a sample subsyste m clock oscillation circuit that are measured using a our company -designated oscillation characteristics ev aluation board and external components with circuit constant values with which the oscillator vend or confirmed normal and stable oscillation. table 2 characteristics of a sample subsystem clock oscillator circuit with a crystal resonator nominal frequency vendor name resonator circuit constant operating voltage range [v] oscillation stabilization time remarks c3 [pf] c4 [pf] rf2 [ ? ] rd2 [ ? ] typ [s] max [s] 32.768 khz epson toyocom mc-306 10 10 open 330k 2.2 to 3.6 1.0 3.0 cl=7.0pf the oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillator ci rcuit is executed plus the time interval that is required for the oscillation to get stabilized after the hold mode is released (see figure 4). note : the traces to and from the components that are invo lved in oscillation should be kept as short as possible as the oscillation characteristics ar e affected by their trace pattern. figure 1. cf oscillator circuit figure 2. xt oscillator circuit figure 3. ac timing measurement point c3 rd2 c4 x?tal xt2 xt1 rf2 0.5v dd c1 c2 cf cf2 cf1 rd1 rf1
LC88FC3J0A www.onsemi.com 44 figure 4. oscillation stabilization time timing charts reset time and oscillation stabilization time operating v dd lower limit hold release and oscillation stabilization time tmsx'tal tmscf i n t erna l rc oscillation cf1, cf2 xt1, xt2 state hold halt instruction execution hold release no hold release signal hold re l ease s i gna l va lid interrupt operation t ms x ' t a l t ms cf v dd 0v reset time power resb internal rc oscillation cf1, cf2 xt1, xt2 operating mode unpredictable reset i n iti a li za ti on instruction execution user instruction execution
LC88FC3J0A www.onsemi.com 45 figure 5. reset circuit figure 6. serial i/o waveforms c res v dd r res res note : reset signal must be present when power supply rises. determine the value of c res and r res so that the reset signal is present for 10 ? s after the supply voltage gets stabilized. tsck dataout: data transfer period (sio0 and sio1 only) datain: sioclk: tsckl tsckha thdi tsdi tddo * remarks: dix and dox denote the last bits communicated; x=0 to 32768 dataout: data transfer period (sio0 and sio1 only) di0 di7 dix di8 do0 do7 dox do8 di1 do1 sioclk: datain: tsckhbsy run: di6 do6 tsckhbsy dataout: datain: tsckl tsckh thdi tsdi sioclk:
LC88FC3J0A www.onsemi.com 46 tbuf thd;sta tlow tr thd;dat thigh tf tsu;dat tsu;st a thd;sta tsp tsu;sto p s s r p s : start condition p : stop condition sir : restart condition sda sck figure 7. pulse input timing signal waveform figure 8. i 2 c timing figure 9. recommended filt circuit * take at least 50ms to oscillation to stabilize after pll is started. tpil tpih 1k ? 2.2 ? f cfs=open pc2/filt cfs v ss 1 + -
LC88FC3J0A www.onsemi.com 47 figure 10. waveform observed when on ly por is used (lvd not used) (reset pin : pull-up resistor r res only) ? the por function generates a reset only when power is turned on starting at the v ss level. ? no stable reset will be generated if power is turned on again when the power level does not go down to the v ss level as shown in (a). if such a case is anticipated, use the lvd function together with the por function or implement an external reset circuit. ? a reset is generated only when the power level goes down to the v ss level as shown in (b) and power is turned on again after this condition continues for 100 s or longer. figure 11. waveform observed when both por and lvd functions are used (reset pin : pull-up resistor r res only) ? resets are generated both when power is tu rned on and when the power level lowers. ? a hysteresis width (lvhys) is provided to pr event the repetitions of reset release and entry cycles near the detection level. v dd res# por release voltage (porrl) unknown-state (pouks) (a) (b) reset period reset period 100 s or longer v dd res# lvd hysteresis width (lvhys) unknown-state (lvuks) reset period reset period reset period lvd release voltage (lvdet+lvhys) lvd reset voltage (lvdet)
LC88FC3J0A www.onsemi.com 48 on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidiaries in the united st ates and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a lis ting of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf . scillc reserves the right to make changes with out further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any parti cular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specific ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated fo r each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc pro ducts are not designed, intended, or authorized for use as com ponents in systems int ended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees ar ising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that sci llc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject t oall applicable copyright laws and is not for resale in any manner. figure 12. low voltage detection minimum width (example of momentary power loss / voltage variation waveform) ordering information device package shipping (qty / packing) LC88FC3J0Autj-2h tqfp 100, 14x14 (pb-free / halogen free) 900 / tray jedec v dd lvd reset voltage t lvdw v ss lvd release volta g e lvdet-0.5v

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